The present invention relates to design and fabrication of a chip, and more particularly, to a wafer-level package having multiple dies arranged in a side-by-side fashion and an associated yield improvement method.
When a chip function of a target chip is achieved using a large-sized die, the fabrication of large-sized dies on a wafer will suffer from low yield and high cost. For example, assuming that distribution of defects on a wafer is the same, a die yield of large-sized dies fabricated on the wafer is lower than a die yield of small-sized dies fabricated on the same wafer. In other words, the die yield loss is positively correlated with the die size. If the network switch chips are fabricated using large-sized dies, the production cost of the network switch chips is high due to the high die yield loss. Thus, there is a need for an innovative integrated circuit design which is capable of reducing the yield loss as well as the production cost.